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| 32Mx64 bits Unbuffered DDR SO-DIMM HYMD532M646A(L)6-J/K/H Document Title 32Mx64 bits Unbuffered DDR SO-DIMM Revision History No. 0.1 0.2 0.3 0.4 Defined Target Spec. Defined Cap. Spec. 1) Reflected a "notational" change in module thickness on page 14 - Not Real ! 2) Corrected some typos 1) Corrected some typo - tRAS.min = 45ns for -H(266B) at page 10 2) Modified the side view of module including additional device at page 14 History Draft Date Jan. 2003 Nov. 2003 Apr. 2004 Oct. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ Oct. 2004 1 32Mx64 bits Unbuffered DDR SO-DIMM HYMD532M646A(L)6-J/K/H DESCRIPTION Preliminary Hynix HYMD532M646A(L)6-J/K/H series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memoryarrays. Hynix HYMD532M646A(L)6-J/K/H series consists of four 32Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-epoxy substrate. Hynix HYMD532M646A(L)6-J/K/H series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD532M646A(L)6-J/K/H series is designed for high speed of up to 166MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD532M646A(L)6-J/K/H series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES * * * * * * 256MB (32M x 64) Unbuffered DDR SO-DIMM based on 32Mx16 DDR SDRAM JEDEC Standard 200-pin small outline dual in-line memory module (SO-DIMM) 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 133/166MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock * * * * * * * * Data inputs on DQS centers when write (centered DQ) Data strobes synchronized with output data for read and input data for write Programmable CAS Latency 2 / 2.5 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 8192 refresh cycles / 64ms * ORDERING INFORMATION Part No. HYMD532M646A(L)6-J HYMD532M646A(L)6-K HYMD532M646A(L)6-H VDD=2.5V VDDQ=2.5V Power Supply Clock Frequency 166MHz(*DDR333) 133MHz(*DDR266A) 133MHz(*DDR266B) Interface Form Pactor 200pin Unbuffered SO-DIMM 67.6mm x 31.75mm x 1mm SSTL_2 * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ Oct. 2004 2 HYMD532M646A(L)6-J/K/H PIN DESCRIPTION Pin CK0, /CK0, CK1, /CK1 CS0 CKE0 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 VDD Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Pin VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA VDDID DU NC Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O VDD Identification Flag Do not Use No Connection PIN ASSIGNMENT Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Name VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Name VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC DU VSS NC NC VDD NC NC A12 Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Name VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC DU VSS VSS VDD VDD CKE0 DU A11 Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Name A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS Pin 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Name A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS NC DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS Pin 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Name DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Name DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU Rev. 0.4/ Oct. 2004 3 HYMD532M646A(L)6-J/K/H FUNCTIONAL BLOCK DIAGRAM /CS0 /CS DQS1 DM1 /CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 DM0 LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 D0 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS4 DM4 LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 D2 /CS DQS3 DM3 /CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 DM2 LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 D1 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS6 DM6 LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 D3 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA VDDSPD VDD/VDDQ VREF VSS VDDID . . == . ...= . .. SPD D0 - D3 D0 - D3 D0 - D3 Strap:see Note 4 BA0-BA1 A0 - A12 /RAS /CAS CKE0 /WE BA0-BA1 : SDRAMs D0 - D3 A0 - A12 : SDRAMs D0 - D3 /RAS : SDRAMs D0 - D3 /CAS : SDRAMs D0 - D3 CKE : SDRAMs D0 - D3 /WE : SDRAMs D0 - D3 Notes: DQ wiring may differ from that described in this drawing ; however DQ/DM/DQS relationship are maintained as shown. VDDID strap connections; (for memory device VDD, VDDQ) : Strap out :(open) : VDD=VDDQ Strap In (Vss) : VDD= VDDQ Rev. 0.4/ Oct. 2004 4 HYMD532M646A(L)6-J/K/H ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit o Operating Temperature (Ambient) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER 0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 1.0 x # of Components 260 / 10 C oC V V V mA W oC / Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage VDD VDDQ VIH VIL VTT VREF 2.3 2.3 VREF + 0.15 -0.3 VREF - 0.04 1.15 2.5 2.5 VREF 1.25 2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 1.35 V V V V V V 3 2 1 Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ. AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs VIH(AC) VIL(AC) VID(AC) VIX(AC) VREF + 0.31 VREF - 0.31 0.7 0.5*VDDQ-0.2 VDDQ + 0.6 0.5*VDDQ+0.2 V V V V 1 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. Rev. 0.4/ Oct. 2004 5 HYMD532M646A(L)6-J/K/H AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 V V V V V V V V/ns pF Rev. 0.4/ Oct. 2004 6 HYMD532M646A(L)6-J/K/H CAPACITANCE (TA=25oC, f=100MHz ) Parameter Pin Symbol Min Max Unit Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input / Output Capacitance A0 ~ A12, BA0, BA1 /RAS, /CAS, /WE CKE0, CKE1 /CS0, /CS1 CK0, /CK0, CK1, /CK1 DM0 ~ DM7 DQ0 ~ DQ63, DQS0 ~ DQS7 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIO1 31 31 36 35 20 9 9 35 35 40 39 24 11 11 pF pF pF pF pF pF pF Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT RT=50 Output Zo=50 VREF CL=30pF Rev. 0.4/ Oct. 2004 7 HYMD532M646A(L)6-J/K/H DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Add, CMD, /CS, /CKE Symbol Min. Max Unit Note -8 ILI -8 0 ILO VOH VOL -5 VTT + 0.76 - 8 8 0 5 VTT - 0.76 uA V V 2 IOH = -15.2mA IOL = +15.2mA uA 1 Input Leakage Current CK0, /CK0, CK1, /CK1 CK2, /CK2 Output Leakage Current Output High Voltage Output Low Voltage Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 2.7V Rev. 0.4/ Oct. 2004 8 HYMD532M646A(L)6-J/K/H DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Symbol Test Condition One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle ; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length =2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle All banks idle; Power down mode; CKE=Low, tCK= tCK(min) Vin>=Vih(min) or Vin= 1840 Speed -J -K -H Unit Note Operating Current IDD0 560 480 480 mA Operating Current Precharge Power Down Standby Current Idle Standby Current Idle Standby Current IDD1 720 600 600 mA IDD2P 40 40 40 mA mA IDD2N IDD2F 140 140 mA Idle Quiet Standby Current Active Power Down Standby Current IDD2Q 100 mA IDD3P 48 mA Active Standby Current IDD3N 180 160 160 mA Operating Current IDD4R 1000 840 840 Operating Current IDD4W 1000 880 880 mA Auto Refresh Current IDD5 1120 1040 1040 20 10 1520 1520 mA mA mA Self Refresh Current Operating Current Four Bank Operation IDD6 IDD7 Four bank interleaving with BL=4 Refer to the following page for detailed test condition 4banks active read with activate every 20ns, AP(Auto Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA, 100% DQ, DM and DQS inputs changing twice per clock cycle; 100% addresses changing once per clock cycle Random Read Current IDD7A 1840 1520 1520 mA Rev. 0.4/ Oct. 2004 9 HYMD532M646A(L)6-J/K/H AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol -J(DDR333) Min Max -K(DDR266A) Min Max -H(DDR266B) Min Max Unit Note Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Write to Read Command Delay Auto Precharge Write Recovery+Precharge Time CL = 2.5 CL = 2 tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL 60 72 42 tRCD or tRASmin 18 12 1 18 15 1 2+(tRP/ tCK) 6 7.5 0.45 0.45 -0.7 -0.6 tHPmin -tQHS tCH/L min - 70K 12 12 0.55 0.55 0.7 0.6 0.45 0.55 65 75 45 tRCD or tRASmin 20 15 1 20 15 1 5 7.5 7.5 0.45 0.45 -0.75 -0.75 tHPmin -tQHS tCH/L min - 120K 12 12 0.55 0.55 0.75 0.75 0.5 0.75 70 80 45 tRCD or tRASmin 20 15 1 20 15 1 (tWR/ tCK)+(tR P/tCK) 8 10 0.45 0.45 -0.75 -0.75 tHPmin -tQHS tCH/L min - 120K 12 12 0.55 0.55 0.75 0.75 0.6 0.75 ns ns ns ns ns ns CK ns ns CK CK ns ns CK CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2,3,5,6 2,3,5,6 2,4,5,6 2,4,5,6 6 1, 10 1,9 10 15 16 System Clock Cycle Time Clock High Level Width Clock Low Level Width tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tDV tHZ tLZ tIS tIH tIS tIH tIPW Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Valid Data Output Window Data-out high-impedance window from CK, /CK Data-out low-impedance window from CK, /CK Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width tQH-tDQSQ -0.7 -0.7 0.75 0.75 0.8 0.8 2.2 0.7 0.7 - tQH-tDQSQ -0.75 -0.75 0.9 0.9 1.0 1.0 2.2 0.75 0.75 - tQH-tDQSQ -0.8 -0.8 1.1 1.1 1.1 1.1 2.5 0.8 0.8 - Rev. 0.4/ Oct. 2004 10 HYMD532M646A(L)6-J/K/H AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -J(DDR333) Parameter Symbol Min Max Min Max Min Max -K(DDR266A) -H(DDR266B) Unit Note - continued - Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Note : tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI 0.35 0.35 0.75 0.45 0.45 1.75 0.9 0.4 0 0.25 0.4 2 200 - 1.25 1.1 0.6 0.6 7.8 0.35 0.35 0.75 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 200 - 1.25 1.1 0.6 0.6 7.8 0.35 0.35 0.75 0.6 0.6 2 0.9 0.4 0 0.25 0.4 2 200 - 1.25 1.1 0.6 0.6 7.8 CK CK CK ns ns ns CK CK CK CK CK CK CK us 8 6,7, 11~13 6,7, 11~13 1. 2. 3. 4. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. For command/address input slew rate >=1.0V/ns For command/address input slew rate >=0.5V/ns and <1.0V/ns This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 Delta tIS ps 0 +50 +100 Delta tIH ps 0 0 0 5. 6. 7. 8. 9. CK, /CK slew rates are >=1.0V/ns These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. Rev. 0.4/ Oct. 2004 11 HYMD532M646A(L)6-J/K/H 11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 Delta tDS ps 0 +75 +150 Delta tDH ps 0 +75 +150 12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level mV +280 Delta tDS ps +50 Delta tDH ps +50 13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) Delta tDS ps 0 +50 +100 Delta tDH ps 0 +50 +100 ns/V 0 +/-0.25 +/- 0.5 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. 15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock 16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tCK. Rev. 0.4/ Oct. 2004 12 HYMD532M646A(L)6-J/K/H SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 CKEn /CS /RAS /CAS /WE ADDR A10/ AP BA Note Extended Mode Register Set Mode Register Set Device Deselect H H H X X X L L H L L L X H L H L L X H H L L L X OP code OP code X 1,2 1,2 1 V 1 1 V 1,3 1 V 1,4 X V 1,5 1 1 1 1 No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit L H H H H X H L X X X H X H H H CA H L RA L L L L H L L CA H H L L L L H L H L H L L X H X H X H X V X H H L L X H X H X H X V L L H H X H X H X L X X X 1 1 1 X 1 1 1 X 1 1 Precharge Power Down Mode Entry H L L H X H X V Exit L H L H Active Power Down Mode (Clock Suspend) Entry Exit H L L L H Note : 1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.4/ Oct. 2004 13 HYMD532M646A(L)6-J/K/H PACKAGE DIMENSIONS Front 2.00 mm Component Keepout Area 67.60 mm 2.00 mm 31.75 mm 20.00 mm Side 1 2.0 mm 39 41 199 3.8mm MAX. Back 2 40 42 200 2.0 mm (Front) 1.1mm MAX. # The location and number of additional device can be different from real product Rev. 0.4/ Oct. 2004 14 SERIAL PRESENCE DETECT SPD SPECIFICATION (32Mx64 Unbuffered DDR SO-DIMM) Rev. 0.4/ Oct. 2004 15 HYMD532M646A(L)6-J/K/H SERIAL PRESENCE DETECT Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 41 42 43 44 45 62 63 Function Description Number of Bytes written into serial memory at module manufacturer Total number of Bytes in SPD device Fundamental memory type Number of row address on this assembly Number of column address on this assembly Number of physical banks on DIMM Module data width Module data width (continued) Module voltage Interface levels(VDDQ) DDR SDRAM cycle time at CAS Latency=2.5(tCK) DDR SDRAM access time from clock at CL=2.5 (tAC) Module configuration type Refresh rate and type Primary DDR SDRAM width Error checking DDR SDRAM data width Minimum clock delay for back-to-back random column address(tCCD) Burst lengths supported Number of banks on each DDR SDRAM CAS latency supported CS latency WE latency DDR SDRAM module attributes DDR SDRAM device attributes : General DDR SDRAM cycle time at CL=2.0(tCK) DDR SDRAM access time from clock at CL=2.0(tAC) DDR SDRAM cycle time at CL=1.5(tCK) DDR SDRAM access time from clock at CL=1.5(tAC) Minimum row precharge time(tRP) Minimum row activate to row active delay(tRRD) Minimum RAS to CAS delay(tRCD) Minimum active to precharge time(tRAS) Module row density Command and address signal input setup time(tIS) Command and address signal input hold time(tIH) Data signal input setup time(tDS) Data signal input hold time(tDH) Minimum active / auto-refresh Time (tRC) Minimum auto-refresh to active / auto-refresh command period (tRFC) Maximum cycle time (tCK max) Maximum DQS-DQ skew time (tDQSQ) Maximum read data hold skew factor (tQHS) SPD Revision code Checksum for Bytes 0~62 0.75ns 0.75ns 0.45ns 0.45ns 60ns 72ns 12ns 0.45ns 0.55ns 18ns 12ns 18ns 42ns 6.0ns +/-0.7ns Bin Sort : J(DDR333@CL=2.5), K(DDR266A@CL=2), H(DDR266B@CL=2.5) Function Supported J K 128 Bytes 256 Bytes DDR SDRAM 13 10 1Bank 64 Bits SSTL 2.5V 7.5ns +/-0.75ns Non-ECC 7.8us & Self refresh x16 N/A 1 CLK 2,4,8 4 Banks 2, 2.5 0 1 Differential Clock Input +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock Out 7.5ns +/-0.7ns 7.5ns +/-0.75ns 20ns 15ns 20ns 45ns 256MB 0.9ns 0.9ns 0.5ns 0.5ns Undefined 65ns 75ns 12ns 0.5ns 0.75ns Undefined Initial release 08h 65ns 75ns 12ns 0.5ns 0.75ns 3Ch 48h 30h 2Dh 55h 0.9ns 0.9ns 0.5ns 0.5ns 75h 75h 45h 45h 20ns 15ns 20ns 45ns 48h 30h 48h 2Ah 10ns +/-0.75ns 75h 70h 7.5ns +/-0.75ns 60h 70h H J Hexa Value K 80h 08h 07h 0Dh 0Ah 01h 40h 00h 04h 75h 75h 00h 82h 10h 00h 01h 0Eh 04h 0Ch 01h 02h 20h C0h 75h 75h 00h 00h 50h 3Ch 50h 2Dh 40h 90h 90h 50h 50h 00h 41h 4Bh 30h 32h 75h 00h 00h BFh EAh 41h 4Bh 30h 32h 75h 90h 90h 50h 50h 50h 3Ch 50h 2Dh A0h 75h 75h 75h 2 2 1 1 H Note 36~40 Reserved for VCSDRAM 46~61 Superset Information(may be used in future) Rev. 0.4/ Oct. 2004 16 HYMD532M646A(L)6-J/K/H SERIAL PRESENCE DETECT(continued) Byte # 64 65~71 Function Description Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code Function Supported J K Hynix JEDEC ID Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area H Y M D 5 3 2 M 6 4 6(8K refresh,4Bank) A 6 `-' J K Blank Undefined Undefined H 4Bh H J Hexa Value K ADh 00h 0*h 1*h 2*h 3*h 4*h 5*h 48h 59h 4Dh 44h 35h 33h 32h 4Dh 36h 34h 36h 41h 36h 2Dh 48h 20h 20h 00h 00h 3 3 4 5 5 4Ch H Note 72 Manufacturing location 6 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88~90 91 92 93 94 95~98 99~127 128~255 Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) Manufacture part number (DDR SDRAM) Manufacture part number(Memory density) Manufacture part number(Module Depth) ------- Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -------Manufacture part number(Data width) Manufacture part number(Refresh, # of Bank.) Manufacture part number(Component Generation) Manufacture part number(Component configuration) Manufacture part number(Hyphen) Manufacture part number(Minimum cycle time) Manufacture part number(T.B.D) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may be used in future) Open for customer use Note : 1. The bank address is excluded 2. This value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix's own Module Serial Number System 5. These bytes undefined and coded as `00h' 6. Refer to Hynix Web Site Byte 85~86, Low power part Byte# 85 86 Function Description Manufacture part number(Low power part) Manufacture part number(Component Configuration) Function Supported J K L 6 H J Hexa Value K 4Ch 36h H Note Rev. 0.4/ Oct. 2004 17 |
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